The present application relates generally to structures and methods for packaging power semiconductor devices.
Wide band gap semiconductor devices, such as SiC devices, have the ability to operate at highly elevated temperatures for some power electronics applications, without degrading device performance or developing failure mechanisms that would limit operating life. This attribute has the potential benefit of permitting high power operation in high temperature environments without expensive cooling structures and materials that would be required if lower operating temperatures had to be maintained. However, operating wide band gap power devices at high temperatures puts severe limitations on the packaging, assembly, interconnection materials, processes and structures.
In the past, semiconductor packaging technologies were designed for the known temperature limits of silicon and gallium arsenide devices, which are near the 125° C. to 150° C. range. Packaging structures for such devices typically incorporate polymer materials and wire bonding interconnection technology, which can be used at lower temperatures without sustaining heat damage. Packaging structures incorporating these technologies generally cannot be subjected to continuous exposure of relatively high temperatures without facing issues of degradation and reliability.
Traditional packaging technologies typically employ organic adhesion layers, which often have relatively high CTE values ranging, for example, from about 30 to about 60 ppm/C. For applications involving very cold temperatures or wide thermal cycles, the use of these organic adhesion layers may cause undesirable levels of thermal stress on packaging structures.
Using polymers in packaging structures which are not hermetically sealed may also cause problems in high moisture environments, since polymers tend to absorb moisture. Absorption of moisture can have undesirable effects, including raising the dielectric constants of the polymers and increasing parasitic capacitances.
Packaging approaches that do not contain organic polymer materials are generally complex, costly and have poor electrical performance. These inorganic based packages are generally wire bonded devices mounted onto a ceramic substrate, which includes one or more interconnect structures and die mount down pads. However, incorporating interconnect structures on ceramic substrates generally results in the use of non-optimum thermally conductive ceramic substrate material, which can in turn result in a module having a non-optimum thermal path.
Further, wire bonded devices have a number of disadvantages, including high series electrical resistance, high inductance, high levels of electromagnetic interference (EMI), application of mechanical stress to the devices, and current crowding on the device surface. Other drawbacks of wire bond assemblies include the need for large package height and large substrate footprints to accommodate the wire bond pads on the substrate. In addition, coating wire bonds with dielectrics to achieve voltage isolation can be difficult for a number of reasons, including the shape of the wire bonds, the gold metal generally used to make the bonds, and the extreme fragility of the bonds themselves. The difficulty of achieving dielectric isolation of wire bonds is becoming more of a problem because of the relatively high currents and voltages used for developing high power applications.